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april 2009 rev 3 1/65 1 m29f 200ft, 400ft, 800ft, 160ft m29f 200fb, 400fb, 800fb, 160fb top / bottom boot block 5 v supply flash memory features ? supply voltage ?v cc = 5 v ? access time: 55 ns ? program / erase controller ? embedded byte/word program algorithms ? erase suspend and resume modes ? low power consumption ? standby and automatic standby ? 100,000 program/erase cycles per block ? electronic signature ? manufacturer code: 0x01 ? top device codes: ? m29f200ft: 0x2251 ? m29f400ft: 0x2223 ? m29f800ft: 0x22d6 ? m29f160ft: 0x22d2 ? bottom device codes: ? m29f200fb: 0x2257 ? m29f400fb: 0x22ab ? m29f800fb: 0x2258 ? m29f160fb: 0x22d8 ? rohs packages available ?so44 ?tsop48 ? automotive device grade 3: ? temperature: ?40 to 125 c ? automotive device grade 6: ? temperature: ?40 to 85 c ? automotive grade certified (aec-q100) tsop48 (n) 12 x 20 mm so44 (m) www.numonyx.com
contents m29fxxxft, m29fxxxfb 2/65 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1 address inputs (a0-a19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3 data inputs/outputs (dq8-dq14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 data input/output or address input (dq15a-1). . . . . . . . . . . . . . . . . . . . 19 2.5 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.7 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.8 reset/block temporary unprotect (rp). . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9 ready/busy output (rb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.10 byte/word organization select (byte). . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.11 v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.12 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 block protection and block unprotection. . . . . . . . . . . . . . . . . . . . . . . . . 23 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 read/reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 auto select command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 unlock bypass command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 unlock bypass program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
m29fxxxft, m29fxxxfb contents 3/65 4.6 unlock bypass reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7 chip erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.8 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.9 erase suspend command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10 erase resume command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.11 read cfi query command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 toggle bit (dq6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 alternative toggle bit (dq2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 appendix a block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 appendix b common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 appendix c block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.1 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 appendix d revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
list of tables m29fxxxft, m29fxxxfb 4/65 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. bus operations, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3. bus operations, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 4. commands, 16-bit mode, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5. commands, 8-bit mode, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6. program/erase times and program/erase endurance cycles, m29f160f . . . . . . . . . . . . 31 table 7. program/erase times and program/erase endurance cycles, m29f800f . . . . . . . . . . . . 31 table 8. program/erase times and program/erase endurance cycles, m29f400f . . . . . . . . . . . . 32 table 9. program/erase times and program/erase endurance cycles, m29f200f . . . . . . . . . . . . 32 table 10. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 12. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 13. device capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16. write ac characteristics, write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data. . . 44 table 20. so44 - 44 lead plastic small outline, 500 mils body width, package mechanical data . . . 45 table 21. information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 22. top boot block addresses, m29f160ft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. bottom boot block addresses, m29f160fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24. top boot block addresses, m29f800ft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25. bottom boot block addresses, m29f800fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 26. top boot block addresses, m29f400ft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 27. bottom boot block addresses, m29f400fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 28. top boot block addresses, m29f200ft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 29. bottom boot block addresses, m29f200fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 30. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 31. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 33. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 34. primary algorithm-specific extended query table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 35. security code area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 36. programmer technique bus operations, byte = v ih or v il . . . . . . . . . . . . . . . . . . . . . . . 59 table 37. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
m29fxxxft, m29fxxxfb list of figures 5/65 list of figures figure 1. logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. tsop connections, m29f160f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. tsop connections, m29f800f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. tsop connections, m29f400f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 5. tsop connections, m29f200f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 6. so connections, m29f800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. so connections, m29f400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. so connections, m29f200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. block addresses, m29f160 (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. block addresses, m29f160 (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. block addresses, m29f800 (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. block addresses, m29f800 (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. block addresses, m29f400 (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. block addresses, m29f400 (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. block addresses, m29f200 (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 16. block addresses, m29f200 (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 17. ac measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 19. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 22. reset/block temporary unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 23. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package outline, top view. . . 44 figure 24. so44 ? 44 lead plastic small outline, 500 mils body width, package outline . . . . . . . . . . . 45 figure 25. programmer equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 26. programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 27. in-system equipment block protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 28. in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
description m29fxxxft, m29fxxxfb 6/65 1 description the following overview of the numonyx ? axcell? m29f 5 v flash memory device (m29w160f) refers to the 16-mbit device. however, the information can also apply to lower densities of the m29f device. the m29w160f is a 16 mbit (2 mbit x8 or 1 mbit x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be performed using a single low voltage (4.5 to 5.5 v) supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. each block can be protected independently to prevent accidental program or erase commands from modifying the memory. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the blocks in the memory are asymmetrically arranged, as shown in figure 9.: block addresses, m29f160 (x8) and figure 10.: block addresses, m29f160 (x16) . the first or last 64 kbytes have been divided into four additional blocks. the 16 kbyte boot block can be used for small initialization code to start the microprocessor, the two 8 kbyte parameter blocks can be used for parameter storage and the remaining 32k is a small main block where the application may be stored. chip enable, output enable and write enable signals control the bus operation of the memory. they allow simple connection to most microprocessors, often without additional logic. the memory is offered tsop48 (12 x 20mm) and so44 packages. the memory is supplied with all the bits erased (set to ?1?).
m29fxxxft, m29fxxxfb description 7/65 figure 1. logic diagram table 1. signal names a0-a19 address inputs dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15a?1 data input/output or address input e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output byte byte/word organization select v cc supply voltage v ss ground nc not connected internally ai06849b 20 a0-a19 w dq0-dq14 v cc e v ss 15 g rp dq15a?1 rb byte
description m29fxxxft, m29fxxxfb 8/65 figure 2. tsop connections, m29f160f dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a 17 a 10 dq14 a2 dq12 dq10 dq15a? 1 v cc dq4 dq5 a7 dq7 nc nc ai06850_160 12 1 13 24 25 36 37 48 dq8 nc a 19 a1 a 18 a4 a5 dq1 dq11 g a 12 a 13 a16 a 11 byte a 15 a 14 v ss e a0 rp v ss
m29fxxxft, m29fxxxfb description 9/65 figure 3. tsop connections, m29f800f dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a 17 a 10 dq14 a2 dq12 dq10 dq15a? 1 v cc dq4 dq5 a7 dq7 nc nc ai06850_800 12 1 13 24 25 36 37 48 dq8 nc a1 a 18 a4 a5 dq1 dq11 g a 12 a 13 a16 a 11 byte a 15 a 14 v ss e a0 rp v ss nc
description m29fxxxft, m29fxxxfb 10/65 figure 4. tsop connections, m29f400f dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a 17 a 10 dq14 a2 dq12 dq10 dq15a? 1 v cc dq4 dq5 a7 dq7 nc nc ai06850_400 12 1 13 24 25 36 37 48 dq8 nc a1 a4 a5 dq1 dq11 g a 12 a 13 a16 a 11 byte a 15 a 14 v ss e a0 rp v ss nc nc
m29fxxxft, m29fxxxfb description 11/65 figure 5. tsop connections, m29f200f dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a 10 dq14 a2 dq12 dq10 dq15a? 1 v cc dq4 dq5 a7 dq7 nc nc ai06850_400 12 1 13 24 25 36 37 48 dq8 nc a1 a4 a5 dq1 dq11 g a 12 a 13 a16 a 11 byte a 15 a 14 v ss e a0 rp v ss nc nc nc
description m29fxxxft, m29fxxxfb 12/65 figure 6. so connections, m29f800 dq3 dq9 dq2 dq0 a8 a9 dq6 dq13 a17 dq12 d q10 dq15a? 1 v cc dq4 dq5 dq14 dq7 ai02906_400 1 11 12 22 23 33 34 44 dq8 a6 a3 a2 a7 a1 a4 a5 dq1 dq11 g w byte a10 a16 a12 a13 a11 a15 a14 v ss a0 rp rb v ss e a18
m29fxxxft, m29fxxxfb description 13/65 figure 7. so connections, m29f400 dq3 dq9 dq2 dq0 a8 a9 dq6 dq13 a17 dq12 d q10 dq15a? 1 v cc dq4 dq5 dq14 dq7 ai02906_400 1 11 12 22 23 33 34 44 dq8 a6 a3 a2 a7 a1 a4 a5 dq1 d q11 g w byte a10 a16 a12 a13 a11 a15 a14 v ss a0 rp rb v ss e nc
description m29fxxxft, m29fxxxfb 14/65 figure 8. so connections, m29f200 dq3 dq9 dq2 dq0 a8 a9 dq6 dq13 dq12 d q10 dq15a? 1 v cc dq4 dq5 dq14 dq7 ai02906_400 1 11 12 22 23 33 34 44 dq8 a6 a3 a2 a7 a1 a4 a5 dq1 dq11 g w byte a10 a16 a12 a13 a11 a15 a14 v ss a0 rp rb v ss e nc nc
m29fxxxft, m29fxxxfb description 15/65 figure 9. block addresses, m29f160 (x8) also see appendix appendix a: block address table for a full listing of the block addresses. figure 10. block addresses, m29f160 (x16) also see appendix appendix a: block address table for a full listing of the block addresses. ai06851_x8_160 16 kbyte 1fffffh 1fc000h 64 kbyte 01ffffh 010000h 64 kbyte 00ffffh 000000h top boot block addresses (x8) 32 kbyte 1f7fffh 1f0000h 64 kbyte 1e0000h 1effffh to t al o f 31 64 kbyt e bl o cks 16 kbyte 1fffffh 1f0000h 64 kbyte 64 kbyte 003fffh 000000h bo t t o m bo o t bl o ck ad d r esses (x8) 32 kbyte 1effffh 01ffffh 64 kbyte 1e0000h 010000h to t al o f 31 64 kbyt e bl o cks 00ffffh 008000h 8 kbyt e 8 kbyt e 1fbfffh 1fa000h 1f9fffh 1f8000h 8 kbyt e 8 kbyt e 007fffh 006000h 005fffh 004000h ai06852_x16_160 8 kword fffffh fe000h 32 kword 0ffffh 0 8000h 32 kword 07fffh 0 0000h top boot block addresses (x16) 16 kword fbfffh f8000h 32 kword f0000h f7fffh to t al o f 31 32 kwo r d bl o cks 8 kword fffffh f8000h 32 kword 32 kword 01fffh 00000h bo t t o m bo o t bl o ck ad d r esses (x16) 16 kword f7fffh 0ffffh 32 kword f0000h 08000h to t al o f 31 32 kwo r d bl o c ks 07fffh 04000h 4 kword 4 kword f dfffh f d000h f cfffh fc000h 4 kword 4 kword 03fffh 03000h 02fffh 02000h
description m29fxxxft, m29fxxxfb 16/65 figure 11. block addresses, m29f800 (x8) also see appendix appendix a: block address table for a full listing of the block addresses. figure 12. block addresses, m29f800 (x16) also see appendix appendix a: block address table for a full listing of the block addresses. ai05463_x8_800 16 kbyte fffffh fc000h 64 kbyte 1ffffh 10000h 64 kbyte 0ffffh 00000h top boot block addresses (x8) 32 kbyte f7fffh f0000h 64 kbyte e0000h effffh to t al o f 15 64 kbyt e bl o cks 16 kbyte fffffh f0000h 64 kbyte 64 kbyte 03fffh 00000h bo t t o m bo o t bl o ck ad d r esses (x8) 32 kbyte effffh 1ffffh 64 kbyte e0000h 10000h to t al o f 15 64 kbyt e bl o cks 0ffffh 08000h 8 kbyt e 8 kbyt e fbfffh fa000h f9fffh f8000h 8 kbyt e 8 kbyt e 07fffh 06000h 05fffh 04000h ai05464_x16_800 8 kword 7ffffh 7 e000h 32 kword 0ffffh 0 8000h 32 kword 07fffh 0 0000h top boot block addresses (x16) 16 kword 7bfffh 78000h 32 kword 70000h 77fffh to t al o f 15 32 kwo r d bl o cks 8 kword 7ffffh 78000h 32 kword 32 kword 01fffh 00000h bo t t o m bo o t bl o ck ad d r esses (x16) 16 kword 77fffh 0ffffh 32 kword 70000h 08000h to t al o f 15 32 kwo r d bl o c ks 07fffh 04000h 4 kword 4 kword 7 dfffh 7 d000h 7 cfffh 7c000h 4 kword 4 kword 03fffh 03000h 02fffh 02000h
m29fxxxft, m29fxxxfb description 17/65 figure 13. block addresses, m29f400 (x8) also see appendix appendix a: block address table for a full listing of the block addresses. figure 14. block addresses, m29f400 (x16) also see appendix appendix a: block address table for a full listing of the block addresses. ai05463_x8_400 16 kbyte 7ffffh 7c000h 64 kbyte 1ffffh 10000h 64 kbyte 0ffffh 00000h top boot block addresses (x8) 32 kbyte 77fffh 70000h 64 kbyte 60000h 6ffffh to t al o f 7 64 kbyt e bl o cks 16 kbyte 7ffffh 70000h 64 kbyte 64 kbyte 03fffh 00000h bo t t o m bo o t bl o ck ad d r esses (x8) 32 kbyte 6ffffh 1ffffh 64 kbyte 60000h 10000h to t al o f 7 64 kbyt e bl o cks 0ffffh 08000h 8 kbyt e 8 kbyt e fbfffh 7a000h 79fffh 78000h 8 kbyt e 8 kbyt e 07fffh 06000h 05fffh 04000h ai5464_x16_400 8 kword 3ffffh 3e000h 32 kword 0ffffh 0 8000h 32 kword 07fffh 0 0000h top boot block addresses (x16) 16 kword 3bfffh 38000h 32 kword 30000h 37fffh to t al o f 7 32 kwo r d bl o cks 8 kword 3ffffh 38000h 32 kword 32 kword 01fffh 00000h bo t t o m bo o t bl o ck ad d r esses (x16) 16 kword 37fffh 0ffffh 32 kword 30000h 08000h to t al o f 7 32 kwo r d bl o c ks 07fffh 04000h 4 kword 4 kword 3 dfffh 3 d000h 3 cfffh 3c000h 4 kword 4 kword 03fffh 03000h 02fffh 02000h
description m29fxxxft, m29fxxxfb 18/65 figure 15. block addresses, m29f200 (x8) also see appendix appendix a: block address table for a full listing of the block addresses. figure 16. block addresses, m29f200 (x16) also see appendix appendix a: block address table for a full listing of the block addresses. ai05463_x8_200 16 kbyte 3ffffh 3c000h 64 kbyte 1ffffh 10000h 64 kbyte 0ffffh 00000h top boot block addresses (x8) 32 kbyte 37fffh 30000h 64 kbyte 20000h 3ffffh to t al o f 3 64 kbyt e bl o cks 16 kbyte 2ffffh 20000h 64 kbyte 64 kbyte 03fffh 00000h bo t t o m bo o t bl o ck ad d r esses (x8) 32 kbyte 2ffffh 1ffffh 64 kbyte 20000h 10000h to t al o f 3 64 kbyt e bl o cks 0ffffh 08000h 8 kbyt e 8 kbyt e 3bfffh 3a000h 39fffh 38000h 8 kbyt e 8 kbyt e 07fffh 06000h 05fffh 04000h ai05464_x16_200 8 kword 1ffffh 1e000h 32 kword 0ffffh 0 8000h 32 kword 07fffh 0 0000h top boot block addresses (x16) 16 kword 3bfffh 18000h 32 kword 10000h 17fffh to t al o f 3 32 kwo r d bl o cks 8 kword 1ffffh 18000h 32 kword 32 kword 01fffh 00000h bo t t o m bo o t bl o ck ad d r esses (x16) 16 kword 17fffh 0ffffh 32 kword 10000h 08000h to t al o f 3 32 kwo r d bl o c ks 07fffh 04000h 4 kword 4 kword 1 dfffh 1 d000h 3 cfffh 1c000h 4 kword 4 kword 03fffh 03000h 02fffh 02000h
m29fxxxft, m29fxxxfb signal descriptions 19/65 2 signal descriptions see figure figure 1. , logic diagram, and table table 1. , signal names, for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a19). the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data inputs/outputs (dq0-dq7). the data inputs/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the program/erase controller. 2.3 data inputs/outputs (dq8-dq14). the data inputs/outputs output the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. 2.4 data input/output or address input (dq15a-1). when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15a?1 low will select the lsb of the word on the other addresses, dq15a?1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address inputs to include this pin when byte is low except when stated explicitly otherwise. 2.5 chip enable (e ). the chip enable, e , activates the memory, allowing bus read and bus write operations to be performed. when chip enable is high, v ih , all other pins are ignored. 2.6 output enable (g ). the output enable, g , controls the bus read operation of the memory.
signal descriptions m29fxxxft, m29fxxxfb 20/65 2.7 write enable (w ). the write enable, w , controls the bus write operation of the memory?s command interface. 2.8 reset/block temporary unprotect (rp ). the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. a hardware reset is achieved by holding reset/block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table table 18. and figure figure 22. , reset/temporary unprotect ac characteristics for more details. holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . 2.9 ready/busy output (rb ). the ready/busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations ready/busy is low, v ol . ready/busy is high-impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy becomes high-impedance. see table table 18. and figure figure 22. , reset/temporary unprotect ac characteristics. the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. 2.10 byte/word organization select (byte ). the byte/word organization select pin is used to switch between the 8-bit and 16-bit bus modes of the memory. when byte/word organization select is low, v il , the memory is in 8- bit mode, when it is high, v ih , the memory is in 16-bit mode. 2.11 v cc supply voltage. the v cc supply voltage supplies the power for all operations (read, program, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from accidentally damaging the data during power up, power down and power surges. if the program/erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.
m29fxxxft, m29fxxxfb signal descriptions 21/65 a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . 2.12 v ss ground. the v ss ground is the reference for all voltage measurements. the two v ss pins of the device must be connected to the system ground.
bus operations m29fxxxft, m29fxxxfb 22/65 3 bus operations there are five standard bus operations that control the device. these are bus read, bus write, output disable, standby and automatic standby. see tables table 2. and table 3. , bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. 3.1 bus read. bus read operations read from the memory cells, or specific registers in the command interface. a valid bus read operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure figure 19. , read mode ac waveforms, and table table 15. , read ac characteristics, for details of when the output becomes valid. 3.2 bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole bus write operation. see figures figure 20. and figure 21. , write ac waveforms, and tables table 16. and table 17. , write ac characteristics, for details of the timing requirements. 3.3 output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . 3.4 standby. when chip enable is high, v ih , the memory enters standby mode and the data inputs/outputs pins are placed in the high-impedance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table table 14. , dc characteristics. during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations until the operation completes. 3.5 automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is reduced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress.
m29fxxxft, m29fxxxfb bus operations 23/65 3.6 special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus operations are intended for use by programming equipment and are not usually used in applications. they require v id to be applied to some pins. 3.7 electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in tables table 2. and table 3. , bus operations. 3.8 block protection and block unprotection. each block can be separately protected against accidental program or erase. protected blocks can be unprotected to allow data to be changed. there are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. block protect and blocks unprotect operations are described in appendix appendix c . table 2. bus operations, byte = v il x = v il or v ih . operation e g w address inputs dq15a?1, a0-a19 data inputs/outputs dq14-dq8 dq7-dq0 bus read v il v il v ih cell address hi-z data output bus write v il v ih v il command address hi-z data input output disable x v ih v ih x hi-z hi-z standby v ih x x x hi-z hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih hi-z 0x01 read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih hi-z 0x51 (m29f200ft) 0x57 (m29f200fb 0x23 (m29f400ft) 0xab (m29f400fb 0xd6 (m29f800ft) 0x58 (m29f800fb 0xd2 (m29f160ft) 0xd8 (m29f160fb)
bus operations m29fxxxft, m29fxxxfb 24/65 table 3. bus operations, byte = v ih x = v il or v ih . operation e g w address inputs a0-a19 data inputs/outputs dq15a?1, dq14-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih x hi-z standby v ih x x x hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih 0x01 read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih 0x2251 (m29f200ft) 0x2257 (m29f200fb 0x2223 (m29f400ft) 0x22ab (m29f400fb 0x22d6 (m29f800ft) 0x2258 (m29f800fb 0x22d2 (m29f160ft) 0x22d8 (m29f160fb)
m29fxxxft, m29fxxxfb command interface 25/65 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. failure to observe a valid sequence of bus write operations will result in the memory returning to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes depending on whether the memory is in 16- bit or 8-bit mode. see either table table 4. , or table 5. , depending on the configuration that is being used, for a summary of the commands. 4.1 read/reset command. the read/reset command returns the memory to its read mode where it behaves like a rom or eprom, unless otherwise stated. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, between bus write cycles before the start of a program or erase operation, to return the device to read mode. once the program or erase operation has started the read/reset command is no longer accepted. the read/reset command will not abort an erase operation when issued while in erase suspend. 4.2 auto select command. the auto select command is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are required to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until a read/reset command is issued. read cfi query and read/reset commands are accepted in auto select mode, all other commands are ignored. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for numonyx is 0020h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29w160et is 22c4h and for the m29w160eb is 2249h. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a12-a19 specifying the address of the block. the other address bits may be set to either v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0-dq7, otherwise 00h is output. 4.3 program command. the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write operations, the final write operation latches the address and data, and starts the program/erase controller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given.
command interface m29fxxxft, m29fxxxfb 26/65 during the program operation the memory will ignore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in tab l e table 6. . bus read operations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory returns to the read mode, unless an error has occurred. when an error occurs the memory continues to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. note that the program command cannot change a bit set at ?0? back to ?1?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. 4.4 unlock bypass command. the unlock bypass command is used in conjunction with the unlock bypass program command to program the memory. when the access time to the device is long (as with some eprom programmers) considerable time saving can be made by using these commands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been issued the memory will only accept the unlock bypass program command and the unlock bypass reset command. the memory can be read as if in read mode. 4.5 unlock bypass program command. the unlock bypass program command can be used to program one address in memory at a time. the command requires two bus write operations, the final write operation latches the address and data, and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the program operation using the program command. a protected block cannot be programmed; the operation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock bypass mode. see the program command for details on the behavior. 4.6 unlock bypass reset command. the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/reset command does not exit from unlock bypass mode. 4.7 chip erase command. the chip erase command can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation appears to start but will terminate
m29fxxxft, m29fxxxfb command interface 27/65 within about 100 s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands. it is not possible to issue any command to abort the operation. typical chip erase times are given in table table 6. . all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the memory to ?1?. all previous data is lost. 4.8 block erase command the block erase command can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50 s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50 s of the last block. the 50 s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register section for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend command. typical block erase times are given in table table 6. . all bus read operations during the block erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost. 4.9 erase suspend command. the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within the erase suspend latency time (refer to tab l e table 6. for value) of the erase suspend command being issued. once the
command interface m29fxxxft, m29fxxxfb 28/65 program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start immediately when the erase resume command is issued. it is not possible to select any further blocks to erase after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. reading from blocks that are being erased will output the status register. it is also possible to issue the auto select, read cfi query and unlock bypass commands during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be accepted. 4.10 erase resume command. the erase resume command must be used to restart the program/erase controller from erase suspend. an erase can be suspended and resumed more than once. 4.11 read cfi query command. the read cfi query command is used to read data from the common flash interface (cfi) memory area. this command is valid when the device is in the read array mode, or when the device is in auto select mode. one bus write cycle is required to issue the read cfi query command. once the command is issued subsequent bus read operations read from the common flash interface memory area. the read/reset command must be issued to return the device to the previous mode (the read array mode or auto select mode). a second read/reset command would be needed if the device is to be put in the read array mode from auto select mode. see appendix appendix b , tables table 30. , table 31. , table 32. , table 33. , table 34. and table 35. for details on the information contained in the common flash interface (cfi) memory area.
m29fxxxft, m29fxxxfb command interface 29/65 table 4. commands, 16-bit mode, byte = v ih x don?t care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. command interface: only uses a?1, a0-a10 and dq0-dq7 to verify the commands; a11-a19, dq8-dq14 and dq15 are don?t care. dq15a?1 is a?1 when byte is v il or dq15 when byte is v ih . read/reset: after a read/reset command, read the memory as normal until another command is issued. auto select: after an auto select command, read manuf acturer id, device id or block protection status. program, unlock bypass program, chip erase, block erase: after these commands read the status register until the program/erase controller completes and the memory returns to read mode. add additional blocks during block erase command with additional bus write operations until timeout bit is set. unlock bypass: after the unlock bypass command issue unlock bypass program or unlock bypass reset commands. unlock bypass reset: after the unlock bypass reset command read the memory as normal until another command is issued. erase suspend: after the erase suspend command read non-erasing memory blocks as normal, issue auto select and program commands on non-erasing blocks as normal. erase resume: after the erase resume command the suspended erase operation resumes, read the status register until the program/erase controller completes and the memory returns to read mode. cfi query: command is valid when device is ready to read array data or when device is in auto select mode. command length bus write operations 1st 2nd 3rd 4th 5th 6th addr addr addr addr addr addr addr addr addr addr addr addr read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 read cfi query 1 55 98
command interface m29fxxxft, m29fxxxfb 30/65 table 5. commands, 8-bit mode, byte = v il x don?t care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. command interface: only uses a?1, a0-a10 and dq0-dq7 to verify the commands; a11-a19, dq8-dq14 and dq15 are don?t care. dq15a?1 is a?1 when byte is v il or dq15 when byte is v ih . read/reset: after a read/reset command, read the memory as normal until another command is issued. auto select: after an auto select command, read manuf acturer id, device id or block protection status. program, unlock bypass program, chip erase, block erase: after these commands read the status register until the program/erase controller completes and the memory returns to read mode. add additional blocks during block erase command with additional bus write operations until timeout bit is set. unlock bypass: after the unlock bypass command issue unlock bypass program or unlock bypass reset commands. unlock bypass reset: after the unlock bypass reset command read the memory as normal until another command is issued. erase suspend: after the erase suspend command read non-erasing memory blocks as normal, issue auto select and program commands on non-erasing blocks as normal. erase resume: after the erase resume command the suspended erase operation resumes, read the status register until the program/erase controller completes and the memory returns to read mode. cfi query: command is valid when device is ready to read array data or when device is in auto select mode. command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 aaa aa 555 55 x f0 auto select 3 aaa aa 555 55 aaa 90 program 4 aaa aa 555 55 aaa a0 pa pd unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 read cfi query 1 aa 98
m29fxxxft, m29fxxxfb command interface 31/65 table 6. program/erase times and program/erase endurance cycles, m29f160f typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100% tested. chip erase, program, and chip program parameters: maximum value measured at worst case conditions for both temperature and v cc after 100,000 program/erase cycles. block erase and erase suspend latency parameters: maximum va lue measured at worst case conditions for both temperature and v cc . table 7. program/erase times and program/erase endurance cycles, m29f800f typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100% tested. chip erase, program, and chip program parameters: maximum value measured at worst case conditions for both temperature and v cc after 100,000 program/erase cycles. block erase and erase suspend latency parameter: maximum value measured at worst case conditions for both temperature and v cc . parameter min typical max unit chip erase ? 25 120 s block erase (64 kbytes) ? 0.8 6 s erase suspend latency time ? 20 25 s program (byte or word) ? 11 200 s chip program (byte by byte) ? 24 120 s chip program (word by word) ? 12 60 s program/erase cycles (per block) 100,000 ? ? cycles data retention 20 ? ? years parameter min typical max unit chip erase ? 12 60 s block erase (64 kbytes) ? 0.8 6 s erase suspend latency time ? 20 25 s program (byte or word) ? 11 200 s chip program (byte by byte) ? 12 ? s chip program (word by word) ? 6 30 s program/erase cycles (per block) 100,000 ? ? cycles data retention 20 ? ? years
command interface m29fxxxft, m29fxxxfb 32/65 table 8. program/erase times and program/erase endurance cycles, m29f400f typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100% tested. chip erase, program, and chip program parameters: maximum value measured at worst case conditions for both temperature and v cc after 100,000 program/erase cycles. block erase and erase suspend latency parameter: maximum value measured at worst case conditions for both temperature and v cc . table 9. program/erase times and program/erase endurance cycles, m29f200f typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100% tested. chip erase, program, and chip program parameters: maximum value measured at worst case conditions for both temperature and v cc after 100,000 program/erase cycles. block erase and erase suspend latency parameter: maximum value measured at worst case conditions for both temperature and v cc . parameter min typical max unit chip erase ? 6 30 s block erase (64 kbytes) ? 0.8 6 s erase suspend latency time ? 20 25 s program (byte or word) ? 11 200 s chip program (byte by byte) ? 6 ? s chip program (word by word) ? 3 15 s program/erase cycles (per block) 100,000 ? ? cycles data retention 20 ? ? years parameter min typical max unit chip erase ? 3 15 s block erase (64 kbytes) ? 0.8 6 s erase suspend latency time ? 20 25 s program (byte or word) ? 11 200 s chip program (byte by byte) ? 4 ? s chip program (word by word) ? 2 8 s program/erase cycles (per block) 100,000 ? ? cycles data retention 20 ? ? years
m29fxxxft, m29fxxxfb status register 33/65 5 status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase suspend when an address within a block being erased is accessed. the bits in the status register are summarized in table table 10. , status register bits. 5.1 data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being programmed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the address just programmed output dq7, not its complement. during erase operations the data polling bit outputs ?0?, the complement of the erased state of dq7. after successful completion of the erase operation the memory returns to read mode. in erase suspend mode the data polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from a ?0? to a ?1? when the program/erase controller has suspended the erase operation. figure figure 1. , data polling flowchart, gives an example of how to use the data polling bit. a valid address is the address being programmed or an address within the block being erased. 5.2 toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations at any address. after successful completion of the operation the memory returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. if any attempt is made to erase a protected block, the operation is aborted, no error is signalled and dq6 toggles for approximately 100 s. if any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and dq6 toggles for approximately 1 s. figure figure 2. , data toggle flowchart, gives an example of how to use the data toggle bit.
status register m29fxxxft, m29fxxxfb 34/65 5.3 error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to ?0? back to ?1? and attempting to do so will set dq5 to ?1?. a bus read operation to that address will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1? 5.4 erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase command. once the program/erase controller starts erasing the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. 5.5 alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/erase controller during erase operations. the alternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to addresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the error. the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased correctly.
m29fxxxft, m29fxxxfb status register 35/65 table 10. status register bits unspecified data bits should be ignored. figure 1. data polling flowchart operation address dq7 dq6 dq5 dq3 dq2 rb program any address dq7 toggle 0 ? ? 0 program during erase suspend any address dq7 toggle 0 ? ? 0 program error any address dq7 toggle 1 ? ? 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no to g g l e 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no to g g l e 0 erase suspend erasing block 1 no toggle 0 ? toggle 1 non-erasing block data read as normal 1 erase error good block address 0 toggle 1 1 no to g g l e 0 faulty block address 0 toggle 1 1 toggle 0 read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
status register m29fxxxft, m29fxxxfb 36/65 figure 2. data toggle flowchart read dq6 start read dq6 twice fail pass ai01370c dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
m29fxxxft, m29fxxxfb maximum rating 37/65 6 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. refer also to the numonyx sure program and other relevant quality documents. table 11. absolute maximum ratings input or output voltage parameter: minimum voltage may undershoot to ?2v during transition and for less than 20ns during transitions. input or output voltage parameter: maximum voltage may overshoot to v cc +2v during transition and for less than 20ns during transitions. symbol parameter min max unit t bias temperature under bias ?50 125 c t stg storage temperature ?65 150 c v io input or output voltage ?0.6 v cc +0.6 v v cc supply voltage ?0.6 6 v v id identification voltage ?0.6 13.5 v
dc and ac parameters m29fxxxft, m29fxxxfb 38/65 7 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in tab l e table 12. , operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 12. operating and ac measurement conditions figure 17. ac measurement i/o waveform figure 18. ac measurement load circuit parameter min max unit v cc supply voltage 4.5 5.5 v ambient operating temperature ?40 125 c load capacitance (c l )3030pf input rise and fall times ? 5 ns input pulse voltages 0 to v cc 0 to v cc v input and output timing ref. voltages v cc /2 v cc /2 v ai04498 v cc 0v v cc /2 ai0449 9 c l c l includes jig capacitance device under test 25k v cc 25k v cc 0.1f
m29fxxxft, m29fxxxfb dc and ac parameters 39/65 table 13. device capacitance sampled only, not 100% tested. table 14. dc characteristics supply current (program/erase) parameter: sampled only, not 100% tested. preliminary data, not yet characterized. symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf symbol parameter test condition min typ max unit i li input leakage current 0v v in v cc ??1 a i lo output leakage current 0v v out v cc ??1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz ?7 10ma i cc2 supply current (standby) e = v cc 0.2v, rp = v cc 0.2v ?60120 a i cc3 supply current (program/erase) program/erase controller active ??20ma v il input low voltage ? 0.5 ? 0.8 v v ih input high voltage ? 0.8v cc ?v cc +0.3 v v ol output low voltage i ol = 1.8ma ? ? 0.45 v v oh output high voltage i oh = ?100 av cc ?0.4 ? ? v v id identification voltage 11.5 ? 12.5 v i id identification current a9 = v id ??100 a v lko program/erase lockout supply voltage ?1.8?2.3v
dc and ac parameters m29fxxxft, m29fxxxfb 40/65 figure 19. read mode ac waveforms table 15. read ac characteristics t elqx t glqx t ehqz and t ghqz parameters: sampled only, not 100% tested. preliminary data, not yet characterized. symbol alt parameter test condition m29f160f unit 55 t avav t rc address valid to next address valid e = v il , g = v il min 55 ns t avqv t acc address valid to output valid e = v il , g = v il max 55 ns t elqx t lz chip enable low to output transition g = v il min 0 ns t elqv t ce chip enable low to output valid g = v il max 55 ns t glqx t olz output enable low to output transition e = v il min 0 ns t glqv t oe output enable low to output valid e = v il max 20 ns t ehqz t hz chip enable high to output hi-z g = v il max 15 ns t ghqz t df output enable high to output hi-z e = v il max 15 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition ?min0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high ? max 3 ns t blqz t flqz byte low to output hi-z ? max 15 ns t bhqv t fhqv byte high to output valid ? max 20 ns ai02922 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a19/ a?1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte
m29fxxxft, m29fxxxfb dc and ac parameters 41/65 figure 20. write ac waveforms, write enable controlled table 16. write ac characteristics, write enable controlled t whrl parameter: sampled only, not 100% tested. preliminary data, not yet characterized. symbol alt parameter m29f160f unit 55 t avav t wc address valid to next address valid min 55 ns t elwl t cs chip enable low to write enable low min 0 ns t wlwh t wp write enable low to write enable high min 30 ns t dvwh t ds input valid to write enable high min 20 ns t whdx t dh write enable high to input transition min 0 ns t wheh t ch write enable high to chip enable high min 0 ns t whwl t wph write enable high to write enable low min 15 ns t avwl t as address valid to write enable low min 0 ns t wlax t ah write enable low to address transition min 30 ns t ghwl output enable high to write enable low min 0 ns t whgl t oeh write enable high to output enable low min 0 ns t whrl t busy program/erase valid to rb low max 20 ns t vchel t vcs v cc high to chip enable low min 50 s ai02923 e g w a0-a19/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
dc and ac parameters m29fxxxft, m29fxxxfb 42/65 figure 21. write ac waveforms, chip enable controlled table 17. write ac characteristics, chip enable controlled t ehrl parameter: sampled only, not 100% tested. preliminary data, not yet characterized. symbol alt parameter m29f160f unit 55 t avav t wc address valid to next address valid min 55 ns t wlel t ws write enable low to chip enable low min 0 ns t eleh t cp chip enable low to chip enable high min 30 ns t dveh t ds input valid to chip enable high min 20 ns t ehdx t dh chip enable high to input transition min 0 ns t ehwh t wh chip enable high to write enable high min 0 ns t ehel t cph chip enable high to chip enable low min 15 ns t avel t as address valid to chip enable low min 0 ns t elax t ah chip enable low to address transition min 30 ns t ghel output enable high chip enable low min 0 ns t ehgl t oeh chip enable high to output enable low min 0 ns t ehrl t busy program/erase valid to rb low max 20 ns t vchwl t vcs v cc high to write enable low min 50 s ai02924 e g w a0-a19/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
m29fxxxft, m29fxxxfb dc and ac parameters 43/65 figure 22. reset/block temporary unprotect ac waveforms table 18. reset/block temporary unprotect ac characteristics t phwl t phgl t rhwl t rhel t rhgl t plyh and t phphh parameters: sampled only, not 100% tested. preliminary data, not yet characterized. symbol alt parameter m29f160f unit 55 t phwl t phel t phgl t rh rp high to write enable low, chip enable low, output enable low min 50 ns t rhwl t rhel t rhgl t rb rb high to write enable low, chip enable low, output enable low min 0 ns t plpx t rp rp pulse width min 500 ns t plyh t ready rp low to read mode max 10 s t phphh t vidr rp rise time to v id min 500 ns ai02931b rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl
package mechanical m29fxxxft, m29fxxxfb 44/65 8 package mechanical figure 23. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package outline, top view drawing is not to scale. table 19. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters typ min max a1.200 a1 0.100 0.050 0.150 a2 1.000 0.950 1.050 b 0.220 0.170 0.270 c 0.100 0.210 cp 0.080 d1 12.000 11.900 12.100 e 20.000 19.800 20.200 e1 18.400 18.300 18.500 e0.500 ? ? l 0.600 0.500 0.700 l1 0.800 a3 0 5 tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp
m29fxxxft, m29fxxxfb package mechanical 45/65 figure 24. so44 ? 44 lead plastic small outline, 500 mils body width, package outline table 20. so44 - 44 lead plastic small outline, 500 mils body width, package mechanical data symbol millimeters typ min max a3.00 a1 0.10 a2 2.69 2.56 2.79 b0.350.50 c0.180.28 d 28.50 28.37 28.63 ddd 0.10 e 16.03 15.77 16.28 e1 12.60 12.47 12.73 e1.27?? l0.79 l1 1.73 8 n44 e1 44 e d c e 1 22 23 b so-f l a1 a ddd a2 l1
part numbering m29fxxxft, m29fxxxfb 46/65 9 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. table 21. information scheme example: m29f200f t 5a m 6 s 2 device type m29f = 5 v density 200 = 2-mbit 400 = 4-mbit 800 = 8-mbit 160 = 16-mbit (not available in so44 package) technology f = 110 nm configuration t = top boot b = bottom boot speed 55 = 55 ns 5a = 55 ns access time (auto grade) only in conjunction with the grade 6 option package m = so 44.525 inch cu n = tsop-1 48 12 x 20 al 4 temperature range 6 = ?40 to 85 c 3 = ?40 to 125 c packing option s = standard packing t = tape & reel packing e = rohs package, standard packing f = rohs package, tape & reel 24 mm packing fab location 2 = numonyx fab.2 (singapore)
m29fxxxft, m29fxxxfb block address table 47/65 appendix a block address table table 22. top boot block addresses, m29f160ft # size (kbytes) address range (x8) address range (x16) 34 16 1fc000h-1fffffh fe000h-fffffh 33 8 1fa000h-1fbfffh fd000h-fdfffh 32 8 1f8000h-1f9fffh fc000h-fcfffh 31 32 1f0000h-1f7fffh f8000h-fbfffh 30 64 1e0000h-1effffh f0000h-f7fffh 29 64 1d0000h-1dffffh e8000h-effffh 28 64 1c0000h-1cffffh e0000h-e7fffh 27 64 1b0000h-1bffffh d8000h-dffffh 26 64 1a0000h-1affffh d0000h-d7fffh 25 64 190000h-19ffffh c8000h-cffffh 24 64 180000h-18ffffh c0000h-c7fffh 23 64 170000h-17ffffh b8000h-bffffh 22 64 160000h-16ffffh b0000h-b7fffh 21 64 150000h-15ffffh a8000h-affffh 20 64 140000h-14ffffh a0000h-a7fffh 19 64 130000h-13ffffh 98000h-9ffffh 18 64 120000h-12ffffh 90000h-97fffh 17 64 110000h-11ffffh 88000h-8ffffh 16 64 100000h-10ffffh 80000h-87fffh 15 64 0f0000h-0fffffh 78000h-7ffffh 14 64 0e0000h-0effffh 70000h-77fffh 13 64 0d0000h-0dffffh 68000h-6ffffh 12 64 0c0000h-0cffffh 60000h-67fffh 11 64 0b0000h-0bffffh 58000h-5ffffh 10 64 0a0000h-0affffh 50000h-57fffh 9 64 090000h-09ffffh 48000h-4ffffh 8 64 080000h-08ffffh 40000h-47fffh 7 64 070000h-07ffffh 38000h-3ffffh 6 64 060000h-06ffffh 30000h-37fffh 5 64 050000h-05ffffh 28000h-2ffffh 4 64 040000h-04ffffh 20000h-27fffh 3 64 030000h-03ffffh 18000h-1ffffh 2 64 020000h-02ffffh 10000h-17fffh 1 64 010000h-01ffffh 08000h-0ffffh 0 64 000000h-00ffffh 00000h-07fffh
block address table m29fxxxft, m29fxxxfb 48/65 table 23. bottom boot block addresses, m29f160fb # size (kbytes) address range (x8) address range (x16) 34 64 1f0000h-1fffffh f8000h-fffffh 33 64 1e0000h-1effffh f0000h-f7fffh 32 64 1d0000h-1dffffh e8000h-effffh 31 64 1c0000h-1cffffh e0000h-e7fffh 30 64 1b0000h-1bffffh d8000h-dffffh 29 64 1a0000h-1affffh d0000h-d7fffh 28 64 190000h-19ffffh c8000h-cffffh 27 64 180000h-18ffffh c0000h-c7fffh 26 64 170000h-17ffffh b8000h-bffffh 25 64 160000h-16ffffh b0000h-b7fffh 24 64 150000h-15ffffh a8000h-affffh 23 64 140000h-14ffffh a0000h-a7fffh 22 64 130000h-13ffffh 98000h-9ffffh 21 64 120000h-12ffffh 90000h-97fffh 20 64 110000h-11ffffh 88000h-8ffffh 19 64 100000h-10ffffh 80000h-87fffh 18 64 0f0000h-0fffffh 78000h-7ffffh 17 64 0e0000h-0effffh 70000h-77fffh 16 64 0d0000h-0dffffh 68000h-6ffffh 15 64 0c0000h-0cffffh 60000h-67fffh 14 64 0b0000h-0bffffh 58000h-5ffffh 13 64 0a0000h-0affffh 50000h-57fffh 12 64 090000h-09ffffh 48000h-4ffffh 11 64 080000h-08ffffh 40000h-47fffh 10 64 070000h-07ffffh 38000h-3ffffh 9 64 060000h-06ffffh 30000h-37fffh 8 64 050000h-05ffffh 28000h-2ffffh 7 64 040000h-04ffffh 20000h-27fffh 6 64 030000h-03ffffh 18000h-1ffffh 5 64 020000h-02ffffh 10000h-17fffh 4 64 010000h-01ffffh 08000h-0ffffh 3 32 008000h-00ffffh 04000h-07fffh 2 8 006000h-007fffh 03000h-03fffh 1 8 004000h-005fffh 02000h-02fffh 0 16 000000h-003fffh 00000h-01fffh
m29fxxxft, m29fxxxfb block address table 49/65 table 24. top boot block addresses, m29f800ft # size (kbytes) address range (x8) address range (x16) 18 16 fc000h-fffffh 7e000h-7ffffh 17 8 fa000h-fbfffh 7d000h-7dfffh 16 8 f8000h-f9fffh 7c000h-7cfffh 15 32 f0000h-f7fffh 78000h-7bfffh 14 64 e0000h-effffh 70000h-77fffh 13 64 d0000h-dffffh 68000h-6ffffh 12 64 c0000h-cffffh 60000h-67fffh 11 64 b0000h-bffffh 58000h-5ffffh 10 64 a0000h-affffh 50000h-57fffh 9 64 90000h-9ffffh 48000h-4ffffh 8 64 80000h-8ffffh 40000h-47fffh 7 64 70000h-7ffffh 38000h-3ffffh 6 64 60000h-6ffffh 30000h-37fffh 5 64 50000h-5ffffh 28000h-2ffffh 4 64 40000h-4ffffh 20000h-27fffh 3 64 30000h-3ffffh 18000h-1ffffh 2 64 20000h-2ffffh 10000h-17fffh 1 64 10000h-1ffffh 08000h-0ffffh 0 64 00000h-0ffffh 00000h-07fffh
block address table m29fxxxft, m29fxxxfb 50/65 table 25. bottom boot block addresses, m29f800fb # size (kbytes) address range (x8) address range (x16) 18 64 f0000h-fffffh 78000h-7ffffh 17 64 e0000h-effffh 70000h-77fffh 16 64 d0000h-dffffh 68000h-6ffffh 15 64 c0000h-cffffh 60000h-67fffh 14 64 b0000h-bffffh 58000h-5ffffh 13 64 a0000h-affffh 50000h-57fffh 12 64 90000h-9ffffh 48000h-4ffffh 11 64 80000h-8ffffh 40000h-47fffh 10 64 70000h-7ffffh 38000h-3ffffh 9 64 60000h-6ffffh 30000h-37fffh 8 64 50000h-5ffffh 28000h-2ffffh 7 64 40000h-4ffffh 20000h-27fffh 6 64 30000h-3ffffh 18000h-1ffffh 5 64 20000h-2ffffh 10000h-17fffh 4 64 10000h-1ffffh 08000h-0ffffh 3 32 08000h-0ffffh 04000h-07fffh 2 8 06000h-07fffh 03000h-03fffh 1 8 04000h-05fffh 02000h-02fffh 0 16 00000h-03fffh 00000h-01fffh
m29fxxxft, m29fxxxfb block address table 51/65 table 26. top boot block addresses, m29f400ft # size (kbytes) address range (x8) address range (x16) 10 16 7c000h-7ffffh 3e000h-3ffffh 9 8 7a000h-7bfffh 3d000h-3dfffh 8 8 78000h-79fffh 3c000h-3cfffh 7 32 70000h-77fffh 38000h-3bfffh 6 64 60000h-6ffffh 30000h-37fffh 5 64 50000h-5ffffh 28000h-2ffffh 4 64 40000h-4ffffh 20000h-27fffh 3 64 30000h-3ffffh 18000h-1ffffh 2 64 20000h-2ffffh 10000h-17fffh 1 64 10000h-1ffffh 08000h-0ffffh 0 64 00000h-0ffffh 00000h-07fffh
block address table m29fxxxft, m29fxxxfb 52/65 table 27. bottom boot block addresses, m29f400fb # size (kbytes) address range (x8) address range (x16) 10 64 70000h-7ffffh 38000h-3ffffh 9 64 70000h-6ffffh 30000h-37fffh 8 64 50000h-5ffffh 28000h-2ffffh 7 64 40000h-4ffffh 20000h-27fffh 6 64 30000h-3ffffh 18000h-1ffffh 5 64 20000h-2ffffh 10000h-17fffh 4 64 10000h-1ffffh 08000h-0ffffh 3 32 08000h-0ffffh 04000h-07fffh 2 8 06000h-07fffh 03000h-03fffh 1 8 04000h-05fffh 02000h-02fffh 0 16 00000h-03fffh 00000h-01fffh
m29fxxxft, m29fxxxfb block address table 53/65 table 28. top boot block addresses, m29f200ft table 29. bottom boot block addresses, m29f200fb # size (kbytes) address range (x8) address range (x16) 6 16 3c000h-3ffffh 1e000h-1ffffh 5 8 3a000h-3bfffh 1d000h-1dfffh 4 8 38000h-39fffh 1c000h-1cfffh 3 32 30000h-37fffh 18000h-1bfffh 2 64 20000h-2ffffh 10000h-17fffh 1 64 10000h-1ffffh 08000h-0ffffh 0 64 00000h-0ffffh 00000h-07fffh # size (kbytes) address range (x8) address range (x16) 6 64 30000h-3ffffh 18000h-1ffffh 5 64 20000h-2ffffh 10000h-17fffh 4 64 10000h-1ffffh 08000h-0ffffh 3 32 08000h-0ffffh 04000h-07fffh 2 8 06000h-07fffh 03000h-03fffh 1 8 04000h-05fffh 02000h-02fffh 0 16 10000h-1ffffh 00000h-01fffh
common flash interface (cfi) m29fxxxft, m29fxxxfb 54/65 appendix b common flash interface (cfi) the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables table 30. , table 31. , table 32. , table 33. , ta bl e 34. and table 35. show the addresses used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is written (see table table 35. , security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by numonyx. issue a read command to return to read mode. note: the common flash interface is only available for temperature range 6 (?40 to 85 c). table 30. query structure overview query data are always presented on the lowest order data outputs. table 31. cfi query identification string query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are ?0?. address sub-section name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing & voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h c2h security code area 64 bit unique device number address data description value x16 x8 10h 20h 0051h "q" 11h 22h 0052h query unique ascii string "qry" "r" 12h 24h 0059h "y" 13h 26h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm amd compatible 14h 28h 0000h 15h 2ah 0040h address for primary algorithm extended query table (see table table 33. ) p = 40h 16h 2ch 0000h 17h 2eh 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 30h 0000h 19h 32h 0000h address for alternate algorithm extended query table na 1ah 34h 0000h
m29fxxxft, m29fxxxfb common flash interface (cfi) 55/65 table 32. cfi query system interface information table 33. device geometry definition address data description value x16 x8 1bh 36h 0045h v cc logic supply minimum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 4.5 v 1ch 38h 0055h v cc logic supply maximum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 5.5 v 1dh 3ah 0000h v pp [programming] supply minimum program/erase voltage na 1eh 3ch 0000h v pp [programming] supply maximum program/erase voltage na 1fh 3eh 0003h typical timeout per single byte/word program = 2 n s8 s 20h 40h 0000h typical timeout for minimum size write buffer program = 2 n sna 21h 42h 000ah typical timeout per individual block erase = 2 n ms 1 s 22h 44h 0000h typical timeout for full chip erase = 2 n ms na 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 256 s 24h 48h 0000h maximum timeout for write buffer program = 2 n times typical na 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 8 s 26h 4ch 0000h maximum timeout for chip erase = 2 n times typical na address data description value x16 x8 27h 4eh 0015h device size = 2 n in number of bytes 2 mbyte 0014h 1 mbyte 0013h 512 kbyte 0012h 256 kbyte 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 async. 2ah 2bh 54h 56h 0000h 0000h maximum number of bytes in multi-byte program or page = 2 n na 2ch 58h 0004h number of erase block regions within the device. it specifies the number of regions within the device containing contiguous erase blocks of the same size. 4 2dh 2eh 5ah 5ch 0000h 0000h region 1 information number of identical size erase block = 0000h+1 1 2fh 30h 5eh 60h 0040h 0000h region 1 information block size in region 1 = 0040h * 256 byte 16 kbyte 31h 32h 62h 64h 0001h 0000h region 2 information number of identical size erase block = 0001h+1 2 33h 34h 66h 68h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8 kbyte
common flash interface (cfi) m29fxxxft, m29fxxxfb 56/65 table 34. primary algorithm-specific extended query table 35h 36h 6ah 6ch 0000h 0000h region 3 information number of identical size erase block = 0000h+1 1 37h 38h 6eh 70h 0080h 0000h region 3 information block size in region 3 = 0080h * 256 byte 32 kbyte 39h 3ah 72h 74h 001eh 0000h region 4 information (2 mbyte) number of identical-size erase block = 001eh+1 31 39h 3ah 72h 74h 000eh 0000h region 4 information (1 mbyte) number of identical-size erase block = 000eh+1 15 39h 3ah 72h 74h 0006h 0000h region 4 information (512 kbyte) number of identical-size erase block = 0006h+1 7 39h 3ah 72h 74h 0002h 0000h region 4 information (256 kbyte) number of identical-size erase block = 0002h+1 3 3bh 3ch 76h 78h 0000h 0001h region 4 information block size in region 4 = 0100h * 256 byte 64 kbyte address data description value x16 x8 address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string ?pri? "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii "1" 44h 88h 0030h minor version number, ascii "0" 45h 8ah 0000h address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) ye s 46h 8ch 0002h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 8eh 0001h block protection 00 = not supported, x = number of blocks in per group 1 48h 90h 0001h temporary block unprotect 00 = not supported, 01 = supported ye s 49h 92h 0002h 0004h 0008h 0160h block protect /unprotect 02 = m29f200 04 = m29f400 08 = m29f800 0f = m29f160 2 4 8 10 4ah 94h 0000h simultaneous operations, 00 = not supported no 4bh 96h 0000h burst mode, 00 = not supported, 01 = supported no 4ch 98h 0000h page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word no
m29fxxxft, m29fxxxfb common flash interface (cfi) 57/65 table 35. security code area address data description x16 x8 61h c3h, c2h xxxx 64 bit: unique device number 62h c5h, c4h xxxx 63h c7h, c6h xxxx 64h c9h, c8h xxxx
block protection m29fxxxft, m29fxxxfb 58/65 appendix c block protection block protection can be used to prevent any operation from modifying the data stored in the flash memory. each block can be protected individually. once protected, program and erase operations on the block fail to change the data. there are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. temporary unprotection is controlled by the reset/block temporary unprotection pin, rp ; this is described in the signal descriptions section. unlike the command interface of the program/erase controller, the techniques for protecting and unprotecting blocks could change between different flash memory suppliers. 9.1 programmer technique the programmer technique uses high (v id ) voltage levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a block follow the flowchart in figure figure 25. , programmer equipment block protect flowchart. during the block protect algorithm, the a19-a12 address inputs indicate the address of the block to be protected. the block will be correctly protected only if a19- a12 remain valid and stable, and if chip enable is kept low, v il , all along the protect and verify phases. the chip unprotect algorithm is used to unprotect all the memory blocks at the same time. this algorithm can only be used if all of the blocks are protected first. to unprotect the chip follow figure figure 26. , programmer equipment chip unprotect flowchart. table table 36. , programmer technique bus operations, gives a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. 9.2 in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp . this can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the flash memory has been fitted to the system. to protect a block follow the flowchart in figure figure 27. , in-system block protect flowchart. to unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. to unprotect the chip follow figure figure 28. , in-system chip unprotect flowchart. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
m29fxxxft, m29fxxxfb block protection 59/65 table 36. programmer technique bus operations, byte = v ih or v il operation e g w address inputs a0-a19 data inputs/outputs dq15a?1, dq14-dq0 block protect v il v id v il pulse a9 = v id , a12-a19 block address others = x x chip unprotect v id v id v il pulse a9 = v id , a12 = v ih , a15 = v ih others = x x block protection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v il , a9 = v id , a12-a19 block address others = x pass = xx01h retry = xx00h block unprotection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v ih , a9 = v id , a12-a19 block address others = x retry = xx01h pass = xx00h
block protection m29fxxxft, m29fxxxfb 60/65 figure 25. programmer equipment block protect flowchart address inputs a19-a12 give the address of the block that is to be protected. it is imperative that they remain stable during the operation. during the protect and verify phases of the algorithm, chip enable e must be kept low, v il . address = block address ai03469b g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il (1) w = v ih e, g = v ih , a0, a6 = v il , a1 = v ih a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il (1) wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
m29fxxxft, m29fxxxfb block protection 61/65 figure 26. programmer equipment chip unprotect flowchart protect all blocks ai03470 a6, a12, a15 = v ih (1) e, g, a9 = v id data w = v ih e, g = v ih address = current block address a0 = v il , a1, a6 = v ih wait 10ms = 00h increment current block n = 0 current block = 0 wait 4s w = v il ++n = 1000 start yes yes no no last block yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
block protection m29fxxxft, m29fxxxfb 62/65 figure 27. in-system equipment block protect flowchart ai03471 write 60h address = block address a0 = v il , a1 = v ih , a6 = v il n = 0 wait 100s write 40h address = block address a0 = v il , a1 = v ih , a6 = v il rp = v ih ++n = 25 start fail pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = block address a0 = v il , a1 = v ih , a6 = v il rp = v id issue read/reset command issue read/reset command write 60h address = block address a0 = v il , a1 = v ih , a6 = v il
m29fxxxft, m29fxxxfb block protection 63/65 figure 28. in-system equipment chip unprotect flowchart ai03472 write 60h any address with a0 = v il , a1 = v ih , a6 = v ih n = 0 current block = 0 wait 10ms write 40h address = current block address a0 = v il , a1 = v ih , a6 = v ih rp = v ih ++n = 1000 start fail pass yes no data = 00h yes no rp = v ih wait 4s read data address = current block address a0 = v il , a1 = v ih , a6 = v ih rp = v id issue read/reset command issue read/reset command protect all blocks increment current block last block yes no write 60h any address with a0 = v il , a1 = v ih , a6 = v ih verify unprotect set-up end
revision history m29fxxxft, m29fxxxfb 64/65 appendix d revision history table 37. document revision history devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. date version revision details 30-march-2009 1 initial release. 1-april-2009 2 corrected block diagram errors; changed read manufacturer code and read device code to tbd. added 55 ns option to speed option in ordering information table. 22-april-2009 3 updated manufacturer code and device id codes in the following locations: ? cover page, ? table 2.: bus operations, byte = vil ? table 3.: bus operations, byte = vih ? table 33.: device geometry definition ? table 34.: primary algorithm-specific extended query table removed the following: ? ?preliminary? and delivery date from cover page; ? 70 ns columns from all ac characteristics tables; ? ?inches? from package manufacturing tables.
m29fxxxft, m29fxxxfb 65/65 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 2009, numonyx, b.v., all rights reserved.

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